Fraunhofer-Gesellschaft

Publica

Hier finden Sie wissenschaftliche Publikationen aus den Fraunhofer-Instituten.

A leak-resilient dual stack scheme for backward-edge control-flow integrity

 
: Zieris, Philipp; Horsch, Julian

:
Volltext urn:nbn:de:0011-n-4974009 (567 KByte PDF)
MD5 Fingerprint: e552f0381f51b5375148862530bb707a
Erstellt am: 28.6.2018


Association for Computing Machinery -ACM-:
ASIACCS 2018, Asia Conference on Computer and Communications Security. Proceedings : Incheon, Republic of Korea, June 04, 2018
New York: ACM, 2018
ISBN: 978-1-4503-5576-6
S.369-380
Asia Conference on Computer and Communications Security (ASIACCS) <2018, Incheon/Korea>
Englisch
Konferenzbeitrag, Elektronische Publikation
Fraunhofer AISEC ()
control-flow integrity; dual stacks; code reuse attack; information leak; information hiding; ASLR; LLVM

Abstract
Manipulations of return addresses on the stack are the basis for a variety of attacks on programs written in memory unsafe languages. Dual stack schemes for protecting return addresses promise an efficient and effective defense against such attacks. By introducing a second, safe stack to separate return addresses from potentially unsafe stack objects, they prevent attacks that, for example, maliciously modify a return address by overflowing a buffer. However, the security of dual stacks is based on the concealment of the safe stack in memory. Unfortunately, all current dual stack schemes are vulnerable to information disclosure attacks that are able to reveal the safe stack location, and therefore effectively break their promised security properties. In this paper, we present a new, leak-resilient dual stack scheme capable of withstanding sophisticated information disclosure attacks. We carefully study previous dual stack schemes and systematically develop a novel design for stack separation that eliminates flaws leading to the disclosure of safe stacks. We show the feasibility and practicality of our approach by presenting a full integration into the LLVM compiler framework with support for the x86-64 and ARM64 architectures. With an average of 2.7% on x86-64 and 0.0% on ARM64, the performance overhead of our implementation is negligible.

: http://publica.fraunhofer.de/dokumente/N-497400.html