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IIP generators to ease analog IC design

Poster presented at Design, Automation & Test in Europe, DATE 2018, 19 - 23 March 2018, Dresden, Germany
: Prautsch, Benjamin; Eichler, Uwe; Reich, Torsten

Poster urn:nbn:de:0011-n-4876863 (1.4 MByte PDF)
MD5 Fingerprint: ecd40c27754c103f5e04abe75cd1c377
Erstellt am: 12.4.2018

2018, 1 S.
Design, Automation & Test in Europe Conference (DATE) <2018, Dresden>
Bundesministerium für Bildung und Forschung BMBF
16ES0240 und 16ESE0110S; Things2Do
"Thin but great silicon to design objects" und "Lowest PoweR technologles and MEmory architectures for IoT"
Bundesministerium für Bildung und Forschung BMBF
Poster, Elektronische Publikation
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()

Semiconductor technology has shown significant progress over the last decades. Digital EDA (electronic design automation) allowed that this progress could be converted to high-performance digital ICs. Analog components are part of Systems-on-Chip (SoC) too, but analog EDA lags far behind. Therefore, a lot of effort was spent to automate analog IC design. Mayor results are constraint-based layout-aware optimization tools using predefined layout templates or pure automation as well as analog generators containing expert knowledge. While optimization is a holistic top-down approach, generators allow parameterized and fast bottom-up generation of critical schematic and layout parts, pre-planned by experienced designers. With IIP Generators, we follow three use cases to ease analog design: 1) design on higher hierarchy levels, 2) development of hierarchical high-level IIPs, and 3) automated design porting due to highly technology-independent blocks down to 22nm.