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Automatic generation of high-performance modular multipliers for arbitrary mersenne primes on FPGAs

: Koppermann, P.; Santis, F. de; Heyszl, J.; Sigl, G.


Institute of Electrical and Electronics Engineers -IEEE-; IEEE Computer Society; IEEE Computer Society, Test Technology Technical Council -TTTC-; IEEE Computer Society, Technical Committee on Security and Privacy:
IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2017. Proceedings : 1-5 May 2017, The Ritz-Carlton, McLean, VA, USA
Piscataway, NJ: IEEE, 2017
ISBN: 978-1-5386-3929-0
ISBN: 978-1-5386-3928-3
ISBN: 978-1-5386-3930-6
International Symposium on Hardware-Oriented Security and Trust (HOST) <10, 2017, McLean/Va.>
Bundesministerium für Bildung und Forschung BMBF
Fraunhofer AISEC ()

Modular multiplication is a fundamental and performance determining operation in various public-key cryptosystems. High-performance modular multipliers on FPGAs are commonly realized by several small-sized multipliers, an adder tree for summing up the digit-products, and a reduction circuit. While small-sized multipliers are available in pre-fabricated high-speed DSP slices, the adder tree and the reduction circuit are implemented in standard logic. The latter operations represent the performance bottleneck to high-performance implementations. Previous works attempted to minimize the critical path of the adder tree by rearranging digit-products on digit-level. We report improved performance by regrouping digit-products on bit-level, while incorporating the reduction for Mersenne primes. Our approach leads to very fast modular multipliers, whose latency and throughput characteristics outperform all previous results. We formalize our approach and provide algorithms to automatically generate high-performance modular multipliers for arbitrary Mersenne primes from any small-sized multipliers.