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Squeezing polynomial masking in tower fields. A higher-order masked AES S-box

: Santis, F. de; Bauer, T.; Sigl, G.


Lemke-Rust, Kerstin:
Smart card research and advanced applications. 15th International Conference, CARDIS 2016 : Cannes, France, November 7-9, 2016; Revised selected papers
Cham: Springer International Publishing, 2017 (Lecture Notes in Computer Science 10146)
ISBN: 978-3-319-54669-8 (Online)
ISBN: 978-3-319-54668-1 (Print)
International Conference on Smart Card Research and Advanced Applications (CARDIS) <15, 2016, Cannes>
Bundesministerium für Bildung und Forschung BMBF
01IS13020A; SIBASE
Fraunhofer AISEC ()

Polynomial masking is a higher-order and glitch-resistant masking scheme to protect cryptographic implementations against side-channel attacks. Polynomial masking was introduced at CHES 2011, while a 1 st-order polynomially masked AES S-box hardware implementation was presented at CHES 2013, and later on improved at TIs 2016. Polynomial masking schemes are advantageous in the way they can be easily adapted to every block-cipher and inherently scaled to any masking order using simple hardware design patterns. As a drawback, they typically have large area, time, and randomness requirements when compared to other masking schemes, e.g. threshold implementations. In this work, we show how tower fields can be perfectly committed to polynomial masking schemes, to reduce both area and randomness requirements of higher-order polynomially masked implementations, with application to AES. We provide ASIC synthesis results up to the 6 th masking order and perform side-channel attacks on a Xilinx Spartan6 FPGA up to the 2 nd masking order.