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Analog IP - with intelligent IP from system to silicon

Presentation held at COSEDA User Group Meeting 2017, Munich
 
: Reich, Torsten

2017, 16 Folien
COSEDA User Group Meeting <2017, Munich>
Englisch
Vortrag
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()
Anfrage beim Institut / Available on request from the institute bibliothek@eas.iis.fraunhofer.de

Abstract
The design of integrated analog circuits is still an almost entirely manual task and therefore expensive, time-consuming, and risky. Intelligent IP (IIP) technology provides unique Analog/Mixed-Signal soft IPs with a high level of analog design automation. IIPs are mainly featured by automated correct-by-construction design generation, technology independence, and configurability. Furthermore, standardized IIP leads to improved design safety. Intelligent IP provides the possibility to automate the design process from transistor-level implementation to system-level behavioral model.

: http://publica.fraunhofer.de/dokumente/N-476880.html