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High speed interfaces for chip communication on interposer based integration

Presentation held at 21st European Microelectronics and Packaging Conference & Exhibition, EMPC 2017, Warsaw, Poland, September 10th to 13th, 2017
 
: Chaudhary, Muhammad Waqas; Heinig, Andy

2017
European Microelectronics and Packaging Conference & Exhibition (EMPC) <21, 2017, Warsaw>
European Commission EC
EFRE; MARS
Ultra-Low-Power Technologien und 3D Integration
Englisch
Vortrag
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()
DDR3; interposer; memory interface
Anfrage beim Institut / Available on request from the institute bibliothek@eas.iis.fraunhofer.de

Abstract
Interposer can offer higher number of interconnect and overall larger bandwidth per unit area and watts as compared to PCB based systems. One of the most commonly discussed high speed interfaces are the memory to processor interfaces which run at high clock rates and transfer data without error. There are a number of constraints to designing these memory systems in PCBs especially the correctly matched on die terminations which not only costs silicon area on the memory die but also costs a lot of power. In this work, it will be shown that silicon interposer based interfaces can support the high speed memory interfaces and can meet the electrical specifications of such interfaces while saving a lot of area DDR3 memory interface is used as the test case to prove this statement.

: http://publica.fraunhofer.de/dokumente/N-474533.html