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UVM-SystemC: Migrating complex verification environments

Presentation held at Design and Verification Conference and Exhibition Europe, DVCon 2017, Munich, Germany, October 16-17, 2017
: Gerth, Stephan; Madhukumar, Akhila

2017, 56 Folien
Design and Verification Conference and Exhibition Europe (DVCon) <2017, Munich>
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()
Anfrage beim Institut / Available on request from the institute

UVM-SystemC is an implementation of the UVM standard for SystemC and is based on the donation of a proof-ofconcept UVM implementation in SystemC to Accellera in 2014. Standardization efforts of UVM for SystemC (named UVMSystemC) have gained momentum to the point that a public review release was done during end of 2016 and a subsequent release is planned for end of 2017 to incorporate the feedback of the previous release. Since the public review release people have been implementing first verification environments, seeking to replace previously used proprietary verification mechanisms. Experiences gained from these first applications of UVMSystemC will be used for constructing complex verification environments in productive development and verification stages. Re-usability and robustness will be shown as the prime advantages of using the UVM-SystemC framework for verification efforts in SystemC. This tutorial will show how a proprietary verification environment is transformed into a UVM-SystemC verification environment using the standardized UVM-mechanisms. This process will be presented in this tutorial over three sections. In the first introductory section, the previously used verification environment will be presented. We will discuss its benefits and drawbacks and the reasons to move to UVM-SystemC. The next step, the migration to the UVM-SystemC verification environment will be presented. We will show how this can be done in a fast manner and where caveats were found. This shows how UVM-SystemC can be used in a productive manner and how re-usability can be achieved to reduce the verification effort while maintaining a high verification quality. The second part will show how randomization using SCV and CRAVE is introduced to further improve verification confidence. Here we will explicitly refer to last year’s UVM-SystemC tutorial about UVM-SystemC and its CRAVE inclusion and show how the presented concepts are applied in a production environment. We will be showing examples where the user can have fine grained control on the quality of randomization by tweaking the seed used for each simulation run. Additionally, techniques to reproduce a failing randomized scenario will be presented to further improve the usefulness of the testbench setup. The audience will gain useful insights on how to use UVM-SystemC/CRAVE/SCV outside of well-known previously shared examples. The final section will discuss the outcome of the migration presented in the previous two sections from a proprietary verification environment to UVM-SystemC including randomization by using CRAVE/SCV. This outcome will be measured by using different key performance indicators (KPIs) such as manual effort, simulation speed and re-usability and thus showing the superiority of the standardized approach. As an informal closing section we will present the ongoing development of the proof-of-concept implementation and the language reference manual to show clearly where UVMSystemC is headed and what has been already achieved in the past activities. As a closing item, future standardization topics, such as functional coverage, within the Accellera Verification Working Group and further application fields of UVM-SystemC will be discussed to give the audience an outlook. The intended audience includes managers, system and verification engineers and architects with a basic knowledge in SystemC and/or UVM, who are interested to further improve their system-level verification practices.