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Circuit level aging simulations predict the long-therm behavior of ICS

How to minimize design margins with accurate advanced transistor degradation models. White Paper
: Lange, André

Volltext urn:nbn:de:0011-n-4741361 (891 KByte PDF)
MD5 Fingerprint: 8bc25eff804f321f89154c496572a575
Erstellt am: 29.11.2017

Erlangen: Fraunhofer IIS, 2017, 7 S.
Bericht, Elektronische Publikation
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()

Reliability is a major criterion for integrated circuits (ICs) in safety critical applications, such as automotive, medical, or aviation electronics. A particular effect that contributes to wear-out is device (i.e. transistor) degradation. Its impact on the circuit behavior can be verified by circuit level aging simulations, which are offered by various EDA vendors. However, reasonable results can only be achieved with accurate and efficient device (i.e. transistor) degradation models. This white paper discusses the state of the art and points out opportunities for improvements.