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Soft error tolerance using HVDQ (Horizontal-Vertical-Diagonal-Queen parity method)

: Ahammed, S.; Sadi, M.S.; Rahman, M.S.; Jürjens, J.

International journal of computer systems science & engineering 32 (2017), Nr.1, S.35-47
ISSN: 0267-6192
Fraunhofer ISST ()

The likelihood of soft errors increases with system complexity, reduction in operational voltages, exponential growth in transistors per chip, increases in clock frequencies and device shrinking. As the memory bit-cell area is condensed, single event upset that would have corrupted only a single bit-cell are now capable of upsetting multiple adjacent memory bit-cells per particle strike. Many of the errors occur when information is transmitted from one node to another node. Detection and correction of these errors is a must for many systems e.g. safety critical systems. To address this issue, a new approach is proposed in this paper to detect and correct multiple bit errors by using Horizontal-Vertical-Diagonal-Queen parity method (HVDQ). The experimental analysis shows the validation of the effectiveness of this approach by comparing its performance with existing approaches.