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Your rails cannot hide from localized EM: How dual-rail logic fails on FPGAs

: Immler, V.; Specht, R.; Unterstein, F.


Fischer, Wieland:
Cryptographic hardware and embedded systems - CHES 2017 : 19th International Conference, Taipei, Taiwan, September 25-28, 2017; Proceedings
Cham: Springer International Publishing, 2017 (Lecture Notes in Computer Science 10529)
ISBN: 978-3-319-66786-7 (Print)
ISBN: 978-3-319-66787-4 (Online)
ISBN: 3-319-66786-6
International Conference on Cryptographic Hardware and Embedded Systems (CHES) <19, 2017, Taipei>
Fraunhofer AISEC ()

Protecting cryptographic implementations against side-channel attacks is a must to prevent leakage of processed secrets. As a cell-level countermeasure, so called DPA-resistant logic styles have been proposed to prevent a data-dependent power consumption. As most of the DPA-resistant logic is based on dual-rails, properly implementing them is a challenging task on FPGAs which is due to their fixed architecture and missing freedom in the design tools. While previous works show a significant security gain when using such logic on FPGAs, we demonstrate this only holds for power-analysis. In contrast, our attack using high-resolution electromagnetic analysis is able to exploit local characteristics of the placement and routing such that only a marginal security gain remains, therefore creating a severe threat. To further analyze the properties of both attack and implementation, we develop a custom placer to improve the default placement of the analyzed AES S-box. Different cost functions for the placement are tested and evaluated w.r.t. the resulting side-channel resistance on a Spartan-6 FPGA. As a result, we are able to more than double the resistance of the design compared to cases not benefiting from the custom placement.