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FPGA-based key generator for the Niederreiter cryptosystem using binary goppa codes

: Wang, Wen; Szefer, Jakub; Niederhagen, Ruben


Fischer, Wieland:
Cryptographic hardware and embedded systems - CHES 2017 : 19th International Conference, Taipei, Taiwan, September 25-28, 2017; Proceedings
Cham: Springer International Publishing, 2017 (Lecture Notes in Computer Science 10529)
ISBN: 978-3-319-66786-7 (Print)
ISBN: 978-3-319-66787-4 (Online)
ISBN: 3-319-66786-6
International Conference on Cryptographic Hardware and Embedded Systems (CHES) <19, 2017, Taipei>
Fraunhofer SIT ()

This paper presents a post-quantum secure, efficient, and tunable FPGA implementation of the key-generation algorithm for the Niederreiter cryptosystem using binary Goppa codes. Our key-generator implementation requires as few as 896,052 cycles to produce both public and private portions of a key, and can achieve an estimated frequency Fmax of over 240 MHz when synthesized for Stratix V FPGAs. To the best of our knowledge, this work is the first hardware-based implementation that works with parameters equivalent to, or exceeding, the recommended 128-bit “post-quantum security” level. The key generator can produce a key pair for parameters m=13, t=119, and n=6960 in only 3.7 ms when no systemization failure occurs, and in 3.5⋅3.7 ms on average. To achieve such performance, we implemented an optimized and parameterized Gaussian systemizer for matrix systemization, which works for any large-sized matrix over any binary field GF(2m). Our work also presents an FPGA-based implementation of the Gao-Mateer additive FFT, which only takes about 1000 clock cycles to finish the evaluation of a degree-119 polynomial at 213 data points. The Verilog HDL code of our key generator is parameterized and partly code-generated using Python and Sage. It can be synthesized for different parameters, not just the ones shown in this paper. We tested the design using a Sage reference implementation, iVerilog simulation, and on real FPGA hardware.