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Interposer based integration to achieve high speed interfaces for ADC application

: Chaudhary, Muhammad Waqas; Heinig, Andy; Dittrich, Michael


Institute of Electrical and Electronics Engineers -IEEE-:
IEEE International 3D Systems Integration Conference, 3DIC 2016 : 8-11 November 2016, San Francisco, California
Piscataway, NJ: IEEE, 2016
ISBN: 978-1-5090-1400-2 (Print)
ISBN: 978-1-5090-1399-9
International 3D Systems Integration Conference (3DIC) <2016, San Francisco/Calif.>
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()

High speed interfaces in traditional Printed Circuit Board based systems are based on serial data communication circuits. Serializing and deserializing circuitries are used on two ends of the chips communicating with each other. The channel can be either between modules over a Backplane, between chip packages on PCB or between dies on an interposer. Backplane and PCB based serial communication has been studied extensively in the literature. But serial data communication analysis between dies in a 2.5D integrated system is yet to be thoroughly analyzed. This paper discusses the channel consisting of interposer lines, and the connection of dies to interposer using copper pillars. It performs the channel extraction using 2D and 3D solvers and describes the channel models. Then it shows the channel simulation results at 10Gb/s data rate using serial circuit models. Finally conclusions are discussed which would enable a better understanding of serial communication in a 2.5D integrated system.