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Heterogeneous Interposer Based Integration of Chips with Copper Pillars and C4 Balls to Achieve High Speed Interfaces for ADC Application

: Dittrich, Michael; Heinig, Andy; Hopsch, Fabian; Trieb, Robert


IEEE Components, Packaging, and Manufacturing Technology Society:
ECTC 2017, the 67th Electronic Components and Technology Conference : 30 May-2 June 2017, Lake Buena Vista, Florida. Proceedings
Piscataway, NJ: IEEE, 2017
ISBN: 978-1-5090-6315-4 (online)
ISBN: 978-1-5090-6316-1 (print)
ISBN: 978-1-5090-4332-3 (USB)
Electronic Components and Technology Conference (ECTC) <67, 2017, Buena Vista/Fla.>
Bundesministerium für Bildung und Forschung BMBF
Mikroelektronik aus Deutschland - Innovationstreiber der Digitalisierung-CATRENE; 16ES0384; SiPoB-3D
Übergreifender Entwurf kompakter Elektroniksysteme – vom Chip bis zur Leiterplatte
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()

Silicon Interposers enable very high routing density in between integrated circuits (ICs) that are fabricated in different technologies like 65 nm for power amplifiers and 14 nm FinFET for highest performance. This is not possible within a System on Chip (SoC). While heterogeneous silicon interposer integration is now used in the first products for processor-memory-integration, it is still rarely used in other fields of application. This paper proposes an approach to integrate an ADC (e.g. fabricated in SiGe bipolar technology) with an existing processing unit like a digital signal processor (DSP) or a field programmable gate array (FPGA) using an interposer and an additional IC for communication. This approach allows to further increase the data rate from the ADC to the processor. It also simplifies the large and costly interface of the ADC. The paper discusses different options of the approach and their impact to the interposer routing. The requirements for the routing of the interposer interconnections are derived from the application, models of the interconnections are extracted with 3D FEM Tools. Finally the interconnections are simulated using accurate Spice models for the IO cells.