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Modelling of pattern formation during electrostatic discharge

Poster presented at Frontiers in Analog CAD, FAC 2017, Frankfurt/Main, 21.-22.07.2017
 
: Scharf, Patrick; Sohrmann, Christoph; Holland, Steffen

:
Poster urn:nbn:de:0011-n-4591080 (481 KByte PDF)
MD5 Fingerprint: e5dbc566484ea87610cdd038ca7ae461
Erstellt am: 3.8.2017


2017, 1 Folie
Workshop "Frontiers in Analog CAD" (FAC) <2017, Frankfurt/Main>
Bundesministerium für Bildung und Forschung BMBF
16ES0301K; RESIST
Resilient Integrated Systems
Englisch
Poster, Elektronische Publikation
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()

Abstract
Pattern formation is a widespread phenomenon in nature, which was already described in 1952 by A. M. Turing [1] for reaction-diffusion systems. It turns out that similar effects also happen in semiconductor devices, when an electrostatic discharge (ESD) event hits the electronics.[2-4] ESD can be considered as one of the main reliability risks of modern electronic systems and causes failure of semiconductor devices by an over current effect. In case of an ESD event the avalanche breakdown leads to a negative differential resistance and the current flow itself causes strong self-heating. Both effects are strongly coupled. The solution of this coupled electro-thermal problem shows a dynamic pattern formation, which is also known as current filament motion. A current filament is very localized and inhomogeneous and causes damage due to gate oxide or junction breakdown much faster than what is expected from the apparent device dimensions. The self-heating then leads to a translational movement which extenuates the problem to some extent. To predict the effectiveness of an ESD protection solution on IC level, it can be desirable to include those effects in a nominal circuit simulation. However, industry standard design systems usually do not include ESD models. Additional user-defined models have to be added. Today, this non-linear electro-thermal problem is mostly solved by a physics-based device simulator such as TCAD (Technology Computer Aided Design). TCAD gives very accurate results, but has an intolerable runtime for a high amount of devices. To improve performance and to enable fast iterations in protection structure design, we suggest a physics-based compact model for the electro-thermal problem. It captures the relevant effects occurring under ESD load at very short simulation times, such as current filament formation, self-heating and filament motion. The major advantage is the possibility to include the model into a circuit simulation and verify IC protection solutions already during the design phase. [1] A. M. Turing, Philosophical Transactions of the Royal Society of London, Vol. 237, No. 641 (1952) [2] D. Pogany et. Al., Thermally-driven motion of current filaments in ESD protection devices, Solid-State Electronics 49 (2005), 421–429 [3] M. Denison et Al., Hot Spot Dynamics in Quasi Vertical DMOS under ESD Stress, ISPSD (2003) [4] R. Xingrong et Al., Motionof current filaments in avalanching PIN diodes, J. Semicond. 34 (4), (2013)

: http://publica.fraunhofer.de/dokumente/N-459108.html