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3D integration of CMOS transistors with ICV-SLID technology

 
: Wieland, R.; Bonfert, D.; Klumpp, A.; Merkel, R.; Nebrich, L.; Weber, J.; Ramm, P.

:

Gessner, T.:
Ninth European Workshop on Materials for Advanced Metallization 2005. Proceedings : 6 - 9 March 2005, Dresden, Germany
Amsterdam: Elsevier, 2005 (Microelectronic engineering 82.2005, 3/4)
S.529-533
European Workshop on Materials for Advanced Metallization (MAM) <9, 2005, Dresden>
Englisch
Konferenzbeitrag, Zeitschriftenaufsatz
Fraunhofer IZM ()

Abstract
3D Integration of CMOS transistors with ICV-SLID technology is reported in this paper. NMOS and PMOS metal gate transistor devices have been further processed by forming deep trench inter-chip-vias and by thinning the substrate to 25 µm remaining silicon thickness. No degradation of transistor behavior found due to the additional 3d-processing steps. Results of the process flow and electrical measurements of transistors on thin silicon are shown in this paper.

: http://publica.fraunhofer.de/dokumente/N-45898.html