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Trends in fan-out wafer and panel level packaging

: Braun, T.; Becker, K.-F.; Wöhrmann, M.; Töpper, M.; Böttcher, L.; Aschenbrenner, R.; Lang, K.-D.


Institute of Electrical and Electronics Engineers -IEEE-; IEEE Components, Packaging, and Manufacturing Technology Society:
International Conference on Electronics Packaging, ICEP 2017 : Takinoyu Hotel, Tendo, Yamagata, Japan, April 19 (Wed.)-22 (Sat.), 2017
Piscataway, NJ: IEEE, 2017
ISBN: 978-4-9902188-3-6
ISBN: 978-4-9902188-2-9
ISBN: 978-1-5090-4888-5 (Print)
International Conference on Electronics Packaging (ICEP) <2017, Tendo/Japan>
Fraunhofer IZM ()

The constant drive to further miniaturization and heterogeneous system integration leads to a need for new packaging technologies that also allow large area processing and 3D integration with strong potential for low cost applications. Here, Fan-Out Wafer Level Packaging [FOWLP] is one of the latest packaging trends in microelectronics. Besides developments to higher and heterogeneous integration the movement to larger formats and panel level packaging to lower cost is noticeable.