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A high-level target-precise model for designing reconfigurable HW tasks

 
: Boden, M.; Rülke, S.; Becker, J.

:

IEEE Computer Society:
20th IEEE International Parallel and Distributed Processing Symposium. Proceedings. CD-ROM : April 25 - 29, 2006, Rhodes Island, Greece
Los Alamitos, Calif.: IEEE Computer Society, 2006
ISBN: 1-4244-0054-6
ISSN: 1530-2075
8 S.
International Parallel and Distributed Processing Symposium (IPDPS) <20, 2006, Rhodes>
Englisch
Konferenzbeitrag
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()
high level synthesis; design pattern; architecture template; Run-Time-Reconfiguration of Hardware; field programmable gate array; FPGA

Abstract
The increasing complexity of embedded digital HW/SW systems, rising chip development and fabrication costs, and a shortened time-to-market require system-level design methods and the use of reconfigurable architectures. Our design method concerns the modelling of a system and its HW tasks at a high abstraction level. Using design patterns and macros, our library-based approach provides a consistent flow from a executable specification to its implementation. These templates ease the efficient application of partially run-time reconfigurable architectures. A case study depicts the high-level modelling of a HW task and its implementation in detail.

: http://publica.fraunhofer.de/dokumente/N-43218.html