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High endurance strategies for hafnium oxide based ferroelectric field effect transistor

: Müller, J.; Polakowski, P.; Müller, S.; Mulaosmanovic, H.; Ocker, J.; Mikolajick, T.; Slesazeck, S.; Flachowsky, S.; Trentzsch, T.

Postprint urn:nbn:de:0011-n-4320374 (526 KByte PDF)
MD5 Fingerprint: 6814718a8edb1c19d273d91bb2ad21cd
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Erstellt am: 26.1.2017

Institute of Electrical and Electronics Engineers -IEEE-:
16th Non-Volatile Memory Technology Symposium, NVMTS 2016 : October 17-19, 2016, Carnegie Mellon University, Pittsburgh, Pennsylvania, U.S.A
Piscataway, NJ: IEEE, 2016
ISBN: 978-1-5090-3523-6
ISBN: 978-1-5090-3522-9
7 S.
Non-Volatile Memory Technology Symposium (NVMTS) <16, 2016, Pittsburgh/Pa.>
Konferenzbeitrag, Elektronische Publikation
Fraunhofer IPMS ()

In this paper potential strategies to overcome the endurance limitations of hafnium oxide based ferroelectric field effect transistors are discussed. These pathways are based on the assumption that the high interfacial field stress and the accompanying charge injection in the metal-ferroelectric-insulator-semiconductor gate stack are the dominant degradation mechanisms during program and erase operation. Three different approaches capable of lowering or eliminating the interfacial field stress are being assessed - lowering the electrical field stress induced by polarization reversal; utilizing low voltage sub-loop operation; altering the capacitive divider within the gate stack.