Fraunhofer-Gesellschaft

Publica

Hier finden Sie wissenschaftliche Publikationen aus den Fraunhofer-Instituten.

IIP framework: A tool for reuse-centric analog circuit design

 
: Prautsch, Benjamin; Eichler, Uwe; Rao, Sunil; Zeugmann, Björn; Puppala, Ajith; Reich, Torsten; Lienig, Jens

:

Institute of Electrical and Electronics Engineers -IEEE-:
13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2016 : 27-30 June 2016, Lisbon, Portugal
Piscataway, NJ: IEEE, 2016
ISBN: 978-1-5090-0489-8
ISBN: 978-1-5090-0490-4
ISBN: 978-1-5090-0491-1
S.83-86
International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) <13, 2016, Lisbon>
Bundesministerium für Bildung und Forschung BMBF
IKT 2020 - Forschung für Innovation; Things2Do
European Commission EC
FP7-JTI; 621221; Things2Do
Englisch
Konferenzbeitrag
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()

Abstract
Current design of analog integrated circuits is still a time-consuming manual process resulting in static analog blocks which can hardly be reused. In order to address this problem, a new framework to ease reuse-centric bottom-up design of analog integrated circuits is introduced. Our IIP Framework (IIP: Intelligent Intellectual Property) enables the development of highly technology-independent analog circuit generators applicable in multiple design environments. IIP Generators are parameterizable descriptions of each view of an analog block, i.e., layout, schematic, and symbol. They allow the adaptation of complex layouts within seconds to minutes in order to incorporate hardly estimable parasitics and further considerations into the design flow. Due to the abstract generator description, valid design data is created for very different technologies such as 28 nm and 180 nm bulk CMOS, 28 nm FD-SOI, and others. The design experiment shows that procedural generators can be an effective tool for the efficient design of analog integrated circuits.

: http://publica.fraunhofer.de/dokumente/N-426412.html