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Modelling current filamentation in Circuit Simulation

Presentation held at 10th International Electrostatic Discharge Workshop, IEW 2016, Tutzing, Germany, May 17 - 19, 2016
: Scharf, Patrick; Sohrmann, Christoph; Holland, Steffen

Präsentation urn:nbn:de:0011-n-4235446 (1.0 MByte PDF)
MD5 Fingerprint: cd27e0569f543f13e32153304a311f98
Erstellt am: 30.11.2016

2016, 24 Folien
International Electrostatic Discharge Workshop (IEW) <10, 2016, Tutzing>
Bundesministerium für Bildung und Forschung BMBF
RESilient Integrated SysTems
Vortrag, Elektronische Publikation
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()

Electrostatic discharge (ESD) can be considered as one of the primary reliability risks of today’s electronic systems and causes failure of semiconductor devices by an over current effect. In case of an ESD event the avalanche breakdown leads to current filamentation and self-heating. This results in very localized damage which typically manifests in leakage current due to gate oxide breakdown or junction damage. In a nominal circuit simulation those effects are not included, so it is required to use additional models. However, current conduction is a non-linear problem and can only be solved by using a physics-based device simulator like TCAD (Technology Computer Aided Design). TCAD gives very accurate results, but only for single devices and has an intolerable runtime. To improve the performance and to enable a fast optimization process during the design phase of a protection structure, we suggest a physics-based compact model capturing the relevant effects occurring under ESD load. One major advantage is the possibility to include the model into a circuit simulation.