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2016
Conference Paper
Titel
Maskless reduction of crosstalk suitable for flexible electronics
Abstract
In order to improve the cut-off frequency in digital circuits a reduction of parasitic capacitances is requested. In this article we present a maskless integration process to reduce crosstalk by patterning the dielectric layer in the field region of the transistor template. Additionally, a method for structuring the semiconducting layer in the field region by lift-off technique is shown. All process steps are limited to a maximum temperature of 115°C aiming at the compatibility with flexible substrates.