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Towards risk aware NoCs for data protection in MPSoCs

: Sepulveda, J.; Florez, D.; Fernandes, R.; Marcon, C.; Gogniat, G.; Sigl, G.


Institute of Electrical and Electronics Engineers -IEEE-:
11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip, ReCoSoc 2016 : June 27-29, 2016, Tallinn, Estonia
Piscataway, NJ: IEEE, 2016
ISBN: 978-1-5090-2520-6
ISBN: 978-1-5090-2521-3
International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoc) <11, 2016, Tallinn>
Fraunhofer AISEC ()

Multi-Processors Systems-on-Chip (MPSoCs), as a key technology enabler of the new computation paradigm Internet-of-Things (IoT), are currently exposed to attacks. Malicious applications can be downloaded at runtime to the MPSoC, infecting IP-blocks connected to a Network-on-Chip (NoC) and opening doors to perform Timing Side Channel Attacks (TSCA). By monitoring the NoC traffic, an attacker is able to infer the sensitive information, such as secret keys. Previous works have shown that NoC routing can be used to avoid attacks. In this paper we propose GRaNoC, a NoC architecture able to monitor and evaluate the risk of the communication paths inside the NoC. Sensitive traffic is exchanged to minimal low-risk paths defined at runtime. We propose five types of dead-lock free risk-aware routing algorithm and evaluate the security, performance and cost under several synthetic and SPLASH-2 benchmarks. We show that our architecture is able to guarantee secure paths during runtime while adding only low cost and performance penalties to the MPSoC.