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Foldable fan-out wafer level packaging

: Braun, T.; Becker, K.-F.; Raatz, S.; Minkus, M.; Bader, V.; Bauer, J.; Aschenbrenner, R.; Kahle, R.; Georgi, L.; Voges, S.; Wöhrmann, M.; Lang, K.-D.


Institute of Electrical and Electronics Engineers -IEEE-; IEEE Components, Packaging, and Manufacturing Technology Society:
IEEE 66th Electronic Components and Technology Conference, ECTC 2016. Proceedings : 31 May-3 June 2016, Las Vegas, Nevada, USA
Los Alamitos, Calif.: IEEE Computer Society Conference Publishing Services (CPS), 2016
ISBN: 978-1-5090-1205-3 (Print)
ISBN: 978-1-5090-1204-6 (Online)
ISBN: 978-1-5090-1203-9
Electronic Components and Technology Conference (ECTC) <66, 2016, Las Vegas/Nev.>
Fraunhofer IZM ()

The constant drive to further miniaturization and heterogeneous system integration leads to a need for new packaging technologies that also allow large area processing and 3D integration with strong potential for low cost applications. Here, Fan-Out Wafer Level Packaging [FOWLP] is one of the latest packaging trends in microelectronics. For FOWLP known good bare dies are embedded into mold compound forming a reconfigured wafer. A redistribution layer is applied on the reconfigured wafer and routes the die pads to the space around and on the die. After bump formation and package singulation by dicing an SMD compatible package is completed. The technology can be also used for multi-chip packages or System in Package (SiP). 3D integration is typically done by package on package (PoP) stacking where the electrical 3D routing is done by through mold vias or vertical interconnect elements [VIE] and a redistribution layer on both sides of the FOWLP.