Hier finden Sie wissenschaftliche Publikationen aus den Fraunhofer-Instituten.

Design challenges in interposer-based 3-D memory logic interface

: Heinig, A.; Chaudhary, M.W.; Fischbach, R.; Dittrich, M.


Advancing microelectronics 43 (2016), Nr.2, S.18-21
ISSN: 2222-8748
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()

Further improvements in system performance are often limited by the achievable bandwidth between processor and memory. In this paper we look at interposer-based and stacked solutions to integrate processor and 3D memory into a high performance system. The comparison is made for different technological decisions, design problems faced for choosing a certain 3D memory type from Wide IO/1-2, High bandwidth memory (HBM) and Hybrid Memory Cube (HMC). Logic die size, metal layers and material of interposer affected by routing requirements of memory systems are discussed.