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Reliability evaluation of Si-dies due to assembly issues

: Naumann, F.; Gottschalk, V.; Burchard, B.; Altmann, F.


Microelectronics reliability 64 (2016), S.266-269
ISSN: 0026-2714
Fraunhofer IMWS ()

Silicon based semiconductor devices are stressed during fabrication, handling and packaging with significant thermal and mechanical loadings. In worst cases, these induced loadings can cause initial chip damage leading to electrical failure or fracture of the Si-die during further process steps or application. In order to evaluate the risk of pre-damage during assembly, a case study of potential failure modes taking pick-and-place processes into account was performed. Therefore, pre-damaged samples using a misaligned pick-and-place setup were generated. Afterwards, methods of microstructural crack analyses and mechanical strength testing were applied to evaluate the damage impact of the generated needle imprint. In addition, finite element analyses in combination with fracture mechanical approaches were combined to evaluate the failure probability of Si-dies during the following assembly or thermal cycling steps.