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Agnostic UVM-XX testbench generation

Replace XX (almost) as you see fit!
: Andersen, Jacob; Gerth, Stephan; Dughetti, Filippo

Design and Verification Conference and Exhibition Europe, DVCon 2016 : October 19 - 20, 2016, Munich, Germany
Munich, 2016
8 S.
Design and Verification Conference and Exhibition Europe (DVCon) <2016, Munich>
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()
SystemVerilog; UVM; UVM-SC; SystemC; Testbench Generation; Constrained Random Verification

Code generation or model driven software development has always had his place within the field of ASIC verification due to the obvious advantages with respect to time savings, complexity reduction, less bugs/errors etc. Typically, model driven software development has been used for generating RTL implementation for registers, register documentation, self-contained register tests from abstract specifications such as IP-XACT. Over the last couple of years generation of testbenches implemented in UVM have been widely introduced within the field by several contributors. This paper tries to leverage all of this previous work and introduce a layered abstraction for UVM testbenches which makes it possible to generate UVM-SystemVerilog (UVM-SV) and UVM-SystemC (UVM-SC) based testbenches from the same abstract specification. Especially UVM-SystemC enables the reuse of testbenches, e.g. from concept level down to Hardware-in-the-loop (HiL) approaches.