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Demonstrating an FPGA implementation of a full HD real-time HEVC decoder with memory optimizations for range extensions support

: Stabernack, B.; Möller, J.; Hahlbeck, J.; Brandenburg, J.


Cerisier, S. ; Institute of Electrical and Electronics Engineers -IEEE-; European Electronic Chips & Systems design Initiative -ECSI-, Gieres:
Conference on Design and Architectures for Signal and Image Processing, DASIP 2015. Proceedings : Cracow, Poland, 23 - 25 September 2015
Piscataway, NJ: IEEE, 2015
ISBN: 979-10-92279-10-8
ISBN: 978-1-4673-7737-9
ISBN: 978-1-4673-7739-3
ISBN: 979-10-92279-11-5
Conference on Design and Architectures for Signal and Image Processing (DASIP) <2015, Cracow>
Fraunhofer HHI ()

The novel High Efficiency Video Coding (HEVC) standard targets a broad set of different video formats ranging from QVGA up to Ultra-HD (4Kp60) resolutions. Especially the high spatial and temporal resolutions combined with the high algorithmic complexity makes implementing encoders and decoders a challenging task. Existing software based implementations on multi-core CPUs and/or DSPs suffer from real-Time constraints, power dissipation and hardware costs of these systems. In this paper a hardware implementation of a Full HD capable H.265/HEVC video decoder is presented targeting these constraints. The demonstrated video decoder incorporates recent standard improvements, namely H.265/HEVC version 2, by supporting enhanced video format range extensions for high quality video applications.