Hier finden Sie wissenschaftliche Publikationen aus den Fraunhofer-Instituten.

Development of a low temperature SiC protection layer for post-CMOS MEMS fabrication utilizing vapour release technologies

: Walk, Christian; Chen, Yizhou; Vidovic, Nino; Kuhl, Andreas; Görtz, Michael; Vogt, H.

Hoffmann, Martin (Hrsg.) ; VDE/VDI-Gesellschaft Mikroelektronik, Mikro- und Feinwerktechnik -GMM-:
Mikro-Nano-Integration. Beiträge des 6. GMM-Workshops 2016. CD-ROM : 5. - 6. Oktober 2016 in Duisburg
Berlin: VDE-Verlag, 2016 (GMM-Fachbericht 86)
ISBN: 978-3-8007-4278-3
ISBN: 3-8007-4278-0
Workshop Mikro-Nano-Integration <6, 2016, Duisburg>
Fraunhofer IMS ()
post-CMOS; MEMS; vapour HF; etching barrier; SiC; release etch

In post-CMOS processing a sufficient protection of the underlying CMOS structures, while applying sacrificial layer release technologies to realize free standing MEMS, is required. In this work, a low temperature Silicon Carbide (SiC) process at 300 C by Inductively Coupled Plasma Chemical Vapour Deposition (ICPCVD) has been developed. It has been demonstrated, that SiC provides an excellent protection character in HF=H2O vapour mixtures. For proof of principle, perforated free-standing SiC-structures with a layer thickness of less than 200 nm and 80 mm in diameter have successfully been released in a vapour etch process.