Hier finden Sie wissenschaftliche Publikationen aus den Fraunhofer-Instituten.

Ceramic substrate technology for wafer level packaging of MEMS

: Ziesche, Steffen; Ihle, Martin; Gabler, Felix; Roscher, Frank


Institute of Electrical and Electronics Engineers -IEEE-:
39th International Spring Seminar on Electronics Technology, ISSE 2016 : Printed electronics and smart textiles, 18-22 May 2016, Pilsen, Czech Republic
Piscataway, NJ: IEEE, 2016
ISBN: 978-1-5090-1389-0 (Online)
ISBN: 978-1-5090-1390-6 (Print)
International Spring Seminar on Electronics Technology (ISSE) <39, 2016, Pilsen>
Fraunhofer IKTS ()
Fraunhofer ENAS ()
LTCC; multilayer ceramic; MEMS; wafer level packaging

The contribution deals with a new wafer level based packaging technology for MEMS. Wafer level packages have advantages compared to standard packaging technologies (miniaturization, cost reduction due to work in multiple panels, optimization of functional parameters). Ceramic packaging technologies offer additional advantages compared to established glass based wafer level packaging. Some examples are a multilayer substrate buildup, a possible integration of passive components (R, L, C) resp. of cavities or channels into the ceramic and a cost efficient manufacturing. The contribution will broach the technologies of ceramic substrate preparation, of component joining and will comment on the advantages of a ceramic solution.