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Guest Editors Introduction: Robust 3-D Stacked ICs

: Khursheed, S.; Vivet, P.; Hopsch, F.; Marinissen, E.J.


IEEE design & test 33 (2016), Nr.3, S.6-7
ISSN: 2168-2356
ISSN: 0740-7475
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()

Three dimensional integrated circuits (ICs) have emerged as a promising technology that complements CMOS scaling through die stacking and allows higher transistor density, heterogeneous technology integration, and smaller footprint than 2-D ICs. Despite potential advantages, a major obstacle to their proliferation is insufficient understanding of challenges caused by die stacking, and in particular due to thermal stress, reliability and physical failure analysis, all of which present exciting research opportunities for the design and test community. This special section is our attempt to provide better understanding of these challenges, and solutions that are currently being developed. We also recognized a growing need for a terminology overview to understand various acronyms and terminologies related to 3-D ICs and interconnect technology.