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Model abstraction of 3D-integrated/interposer-based high performance systems for faster (thermal) simulation

: Heinig, Andy; Papaioannou, Dimitrios; Fischbach, Robert

Postprint urn:nbn:de:0011-n-4023964 (604 KByte PDF)
MD5 Fingerprint: 7327bcb83a38691738927774464a3039
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Erstellt am: 15.7.2016

Institute of Electrical and Electronics Engineers -IEEE-; IEEE Components, Packaging, and Manufacturing Technology Society:
15th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, ITherm 2016. Proceedings : May 31 - June 03, 2016, Las Vegas, Nevada, USA
Piscataway, NJ: IEEE, 2016
ISBN: 978-1-4799-5266-3
ISBN: 978-1-4673-8121-5
ISBN: 978-1-4673-8120-8
ISBN: 978-1-4673-8122-2
Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm) <15, 2016, Las Vegas/Nev.>
Konferenzbeitrag, Elektronische Publikation
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()

Complex, high-integrated and high-performance microelectronic systems that include an interposer-solution become more and more dominant in the field of advanced 2.5/3D system integration. In such systems, for example required in network and image processing applications, the different ICs (e.g. processors and memories) are placed on a silicon interposer, which allow shorter interconnect lines between the elements, improving the signal transmission. The example system used throughout this paper combines an ASIC for signal processing with a high-performance memory. These two chips are placed as bare dies side-by-side on a silicon interposer using copper pillars. The interposer itself is located on a PCB. The good thermal conductivity of the copper structures within the interposer (i.e., top and bottom metal layers and the through-silicon-vias), in combination with the copper pillars underneath the dies, enable a high-performance and effective thermal behavior of the system; the heat produced by the processor and memory dies is dissipated through these elements to the PCB substrate that supports the system. However, in complex microelectronic systems that include arrays of different metal layers, TSVs, copper pillars, solder balls etc., their modeling and simulation can be an expensive procedure. This is especially a problem in early design phases where many different technologies options (e.g., packaging variants) have to be evaluated. Moreover, a real design exploration can be time consuming in many cases. In order to simplify the modeling procedure and speed up simulation, we present an alternative approach to derive simulation models from system descriptions, reduce the simulation time, and ensure the reliability of the obtained results. The array of copper pillars of the system is substituted with simplified blocks with the same volume and material properties. In terms of simulation, the meshing of cuboids and rectangular blocks is easier than meshing cylinders or spheres. The simulation time of the simplified model can be significantly reduced. First simplifications already result in 10-15% shorter simulation time (down to 2 mins reduction). The obtained numerical results are similar to the ones extracted prior to the aforementioned simplifications; the value deviation ranged between 1.5-3% for simulation cases up to 10 W applied power. However, the possible degree of simplification is strongly dependent on the application specific boundary conditions. As an example, for high-power applications; by further increasing the applied power, larger deviations can be observed (up to 7.8% for 25 W power, according to our simulation). Additionally, we propose an efficient solution in order to simulate the hot-spots inside the dies; they are performing complex and high-speed functions that result in heat concentration at specific points of the IC. Finally, another important parameter examined is the influence of the thermal interface material (TIM) in the behavior of the system with respect to the heat dissipated through the system if a heat-sink is included in the model.