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2016
Presentation
Titel
Generator-based design of a 12-Bit DAC soft-IP in 28 nm FD-SOI
Titel Supplements
Presentation held at the Workshop "Design & Reuse "FD-SOI Day", DATE Conference 2016, Dresden, Germany, March 14th, 2016
Abstract
Analog integrated circuit design is still characterized by a variety of manual tasks while the digital design procedure benefits from complete and automatic synthesis flows. Therefore, analog parts of mixed-signal circuits easily cause design failures and require the main effort regarding development time and cost. With our rethought generator approach we implemented a large part of a 12-bit DAC (digital-to-analog converter) as reconfigurable analog circuit generator (analog soft IP) for 28 nm FD-SOI. As the result, we reduce analog design time and improve analog circuit design quality. In addition, we improved yield by utilizing the FD-SOI back gate. Ultimately, in contrast to manual analog design, with our approach we gain analog design reuse.
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