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Co-design of CML IO and interposer channel for low area and power signaling

 
: Chaudhary, Muhammad Waqas; Heinig, Andy

:
Postprint urn:nbn:de:0011-n-3894952 (479 KByte PDF)
MD5 Fingerprint: 64f23ac6ea6304dbaa7f77f47a8e9261
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Erstellt am: 29.4.2016


Brenkuš, J. ; Institute of Electrical and Electronics Engineers -IEEE-; Institute of Electrical and Electronics Engineers -IEEE-, Council on Electronic Design Automation; IEEE Computer Society:
19th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2016. Proceedings : April 20-22, 2016, Košice, Slovakia
Piscataway, NJ: IEEE, 2016
ISBN: 978-1-5090-2466-7
ISBN: 978-1-5090-2468-1 (Print)
ISBN: 978-1-5090-2467-4
S.84-88
International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) <19, 2016, Košice>
European Commission EC
EFRE; MARS
Ultra-Low-Power Technologien und 3D Integration
Englisch
Konferenzbeitrag, Elektronische Publikation
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()

Abstract
In recent years, 2.5D integration of ICs on Interposer is becoming popular for highly integrated miniaturized systems. To combine two or more chips together, there is a lot of communication between the chips and this needs either a very high number of slow channels or numerous high speed channels. To find an optimum number and speed of interposer channels is an important task. In conventional PCB data communication systems, very high speed serial data transmission circuits are used which take a lot of area and power. While in 2.5D systems, area-power are strict constraints and the interposer channel is drastically different from PCB channel in terms of its electrical properties. To enable high bandwidth chip-to-chip interposer communication with low area-power requirements, it is mandatory to co-design the interposer channel and IO circuit. To address the issue, this paper discusses the electrical properties of 2.5D channel segments along with a co-design methodology targeting optimum area-power cost for maximum bandwidth current mode logic differential driver.

: http://publica.fraunhofer.de/dokumente/N-389495.html