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A 4k capable FPGA based high throughput binary arithmetic decoder for H.265/MPEG-HEVC

 
: Hahlbeck, J.; Stabernack, B.

:

Bellido, F.J. ; Institute of Electrical and Electronics Engineers -IEEE-; IEEE Consumer Electronics Society -CE-; Informationstechnische Gesellschaft -ITG-:
IEEE Fourth International Conference on Consumer Electronics - Berlin, ICCE-Berlin 2014 : Berlin, Germany, 7 - 10 September 2014
Piscataway, NJ: IEEE, 2014
ISBN: 978-1-4799-6166-5
ISBN: 978-1-4799-6165-8
S.388-390
International Conference on Consumer Electronics - Berlin (ICCE-Berlin) <4, 2014, Berlin>
Englisch
Konferenzbeitrag
Fraunhofer HHI ()

Abstract
High Efficiency Video Coding (HEVC) is the newest video coding standard approved by the ISO/IEC and ITU-T in January 2013. By providing a video coding efficiency gain of up to 50% compared to its predecessor H.264/MPEG-4 AVC, the complexity of the used algorithms has raised significantly. Targeting video formats with higher spatial and temporal resolutions - e.g. 4Kp60 in broadcast applications - make implementing encoders and decoders a challenging task. A well known bottleneck in the decoder architecture is the Context-Based Adaptive Binary Arithmetic Coding (CABAC), specified as entropy coding method in the H.265/MPEG-HEVC standard. Reaching high throughput for real time applications is a demanding task in terms of context modeling and serial bin-to-bin dependencies in the binary arithmetic coding engine. Especially the context selection and the update of the context model in binary decision mode requires a complex underlying control flow for the decoding process of each syntax element. This paper presents a pure hardware implementation of a Main Profile H.265/MPEG-HEVC compliant entropy decoder. The design has been optimized to achieve real time performance up to 4k video resolutions. By using state-of-the-art FPGA technology, data rates of up to 104 MBit/s can be achieved.

: http://publica.fraunhofer.de/dokumente/N-383345.html