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Low-area reed decoding in a generalized concatenated code construction for PUFs

: Hiller, M.; Kürzinger, L.; Sigl, G.; Müelich, S.; Puchinger, S.; Bossert, M.


Todri-Sanial, A. ; Institute of Electrical and Electronics Engineers -IEEE-; IEEE Computer Society:
IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2015. Proceedings : Montpellier, France, 8-10 July 2015
Los Alamitos, Calif.: IEEE Computer Society Conference Publishing Services (CPS), 2015
ISBN: 978-1-4799-8718-4 (Print)
ISBN: 978-1-4799-8720-7
ISBN: 978-1-4799-8719-1
Annual Symposium on VLSI (ISVLSI) <2015, Montpellier>
Fraunhofer AISEC ()

Physical Unclonable Functions (PUFs) enable secure key storage for integrated circuits and FPGAs. PUF responses are noisy such that error correction is required to generate stable cryptographic keys. One popular approach is to use error-correcting codes. We present an area-optimized VLSI implementation of a recent Generalized Concatenated (GC) code construction using Reed-Muller codes. Reed-Muller codes have the advantage that there exist very efficient decoders. Our new Reed decoding implementation makes extensive use of a circular shift register. The functionality is extended so that it can also handle erasure symbols to improve the error correction capability. The overall GC code decoder occupies less than 110 slices and two block RAMs on an entry-level FPGA, and has a key error probability of 1.5 × 10-9. The slice count is reduced by 50% compared to the reference implementation.