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Fab integrated packaging (FIP): A new concept for high reliability wafer-level chip size packaging
: Töpper, M.; Auersperg, J.; Glaw, V.; Kaskoun, K.; Prack, E.; Keser, B.; Coskina, P.; Jäger, D.; Petter, D.; Ehrmann, O.; Samulewicz, K.; Meinherz, C.; Fehlberg, S.; Karduck, C.; Reichl, H.
|Electronic Components, Assemblies, and Materials Association; IEEE Components, Packaging, and Manufacturing Technology Society:|
ECTC 2000. Proceedings of the 50th Electronic Components & Technology Conference : May 21 - 24, 2000, Las Vegas, Nevada, USA
Piscataway, NJ, USA: IEEE Press, 2000
|Electronic Components and Technology Conference (ECTC) <50, 2000, Las Vegas/Nev.>|
|Fraunhofer IZM ()|
Wafer Level Packaging has the highest potential for future single chip packages. The package is completed directly on the wafer then singulated by dicing for the assembly in a flip chip fashion. All packaging and testing operations of simulated dice will be replaced by whole wafer fabrication and wafer level testing. The result is a technology which leads the way to Fab Integrated Packaging (FIP). An evaluation of the reliability of a new Wafer-Level Chip Scale Package (WL-CSP) was done in the FIP program, a joint development program between Fraunhofer IZM and Motorola. As a CSP the FIP-CSP eliminates underfill operation during flip-chip bonding using high through-put SMT assembly lines. The technological structure of this FIP-CSP is a pad redistributed die with a solder ball array. A stress compensation layer (SCL) embeds the solder balls before second solder balls are stencil printed or placed on top of embedded balls. The reliability of this wafer-level CSP presented here wassimulated and evaluated by test samples. The test chip was a 1 cm×1 cm square chip which was redistributed to an 14×14 ball array with a pitch of 0.5 mm. JEDEC Level 3, 1000 cycles AATC (-55°C/+125°C) and 48 h Autoclave on component level were passed. On board level 1000 hours humidity storage at 85°C (85/85 test) and 1000 cycles -55/+125°C were passed.