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Soft error tolerance using Horizontal-Vertical-Double-Bit diagonal parity method

 
: Rahman, M.S.; Sadi, M.S.; Ahammed, S.; Jürjens, J.

:

Institute of Electrical and Electronics Engineers -IEEE-; Institute of Electrical and Electronics Engineers -IEEE-, Bangladesh Section:
International Conference on Electrical Engineering and Information Communication Technology, ICEEICT 2015. Vol.1 : Savar, Dhaka, Bangladesh, 21 - 23 May 2015
Piscataway, NJ: IEEE, 2015
ISBN: 978-1-4673-6677-9
ISBN: 978-1-4673-6676-2
ISBN: 978-1-4673-6675-5
S.362-367
International Conference on Electrical Engineering and Information Communication Technology (ICEEICT) <2, 2015, Dhaka>
Englisch
Konferenzbeitrag
Fraunhofer ISST ()

Abstract
The likelihood of soft errors increase with system complexity, reduction in operational voltages, exponential growth in transistors per chip, increases in clock frequencies and device shrinking. As the memory bit-cell area is condensed, single event upset that would have formerly despoiled only a single bit-cell are now proficient of upsetting multiple contiguous memory bit-cells per particle strike. While these error types are beyond the error handling capabilities of the frequently used error correction codes (ECCs) for single bit, the overhead associated with moving to more sophisticated codes for multi-bit errors is considered to be too costly. To address this issue, this paper presents a new approach to detect and correct multi-bit soft error by using Horizontal-Vertical-Double-Bit-Diagonal (HVDD) parity bits with a comparatively low overhead.

: http://publica.fraunhofer.de/dokumente/N-379566.html