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Ultra thin chips for miniaturized products

: Jung, E.; Ostmann, A.; Wojakowski, D.; Landesberger, C.; Aschenbrenner, R.; Reichl, H.


Microsystem Technologies 9 (2003), Nr.6-7, S.449-452
ISSN: 0946-7076
Fraunhofer IZM ()

The demand to miniaturize products especially for mobile applications and autonomous systems is continuing to drive the evolution of electronic products and manufacturing methods. One key to miniaturization developed in the past was the use of unpackaged, bare dice. Saving the volume and weight of the package, significant reduction in footprint was achieved. A next step conceived to further the miniaturization is the integration of functions on miniaturized subsystems, i.e. System-in-Package (SiP), in contrast to a full silicon integration (System-on-Chip, SoC). The use of recent manufacturing methods allows to merge the SiP approach with a volumetric integration. Up to now, most of the systems utilize single- or double-sided populated system carriers. Embedding of passive components was a first step forward. A new challenge is to incorporate not only passive components, but active circuitry (IC's) and the necessary thermal management as well. Ultra thin chips (i.e. silicon dies thinned down to similar to50 mum total thickness) lend themselves to reach these goals. Chips with that thickness can be embedded in the dielectric layers of modern laminate PCB's. Micro via technology allows to connect the embedded chip to the outer faces of the system circuitry. As an ultimate goal for microsystem integration, the embedding of optical and fluidical system components can be envisioned. This paper presents the first approach to embed thin silicon dies in to polymeric system carriers. The aspects of embedding and making the electrical contact as well as the thermal management are highlighted. To reach the goal of a vertically stackable "box-of-bricks" type of ultra thin (UT) package, thin silicon chips are embedded and interconnected on a peripheral UT BGA.