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Evaluation of pattern scale stress effects of 28nm technology during wire bond and Cu pillar flip chip assembly

: Kaulfersch, E.; Auersperg, J.; Breuer, D.; Brämer, B.; Rzepka, S.

International Microelectronics and Packaging Society -IMAPS-; Institute of Electrical and Electronics Engineers -IEEE-:
20th European Microelectronics and Packaging Conference & Exhibition, EMPC 2015 : Enabling technologies for a better life and future, Friedrichshafen, Germany, 14-16 September 2015
Piscataway, NJ: IEEE, 2015
ISBN: 978-0-9568086-1-5
ISBN: 978-0-9568086-2-2
6 S.
European Microelectronics and Packaging Conference & Exhibition (EMPC) <20, 2015, Friedrichshafen>
Fraunhofer ENAS ()

Flip chip or wire bonding on highly sensitive low-k and ultra-low-k (ULK) BEoL-structures is an important issue concerning the thermo-mechanical integrity. To assess the thermo-mechanical stress situation in BEoL structures under the loading conditions of wire bonding and pull testing using Finite-element-analyses (FEA), a suitable approach is necessary. In particular, the phenomenon of friction at the bonding surfaces, the heat sources of friction and shock and vibrations have to be considered. These simulations together with experimental findings deliver essential insights into the stress situation within low-k and ULK BEoL structures during bonding and pull tests and, as it is a well described physical model, give basic measurable knowledge on the major factors influencing the thermo-mechanical reliability. Copper instead of Gold wire bonding is introducing much higher mechanical impact to underlying Back-end of line (BeoL) structures and actives like low-k and ultra low-k materials for (BEoL) layers of advanced CMOS technologies because of the higher stiffness and lower ductility of Copper compared to Gold. Increasing stiffness is also an issue for Copper studs replacing solder ball interconnects in the case of flip chip mounting whereby BEoL loading is increasing.