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UVM-SystemC-AMS framework for system-level verification and validation of automotive use cases

: Barnasconi, Martin; Dietrich, Manfred; Einwich, Karsten; Vörtler, Thilo; Chaput, Jean-Paul; Louërat, Marie- Minerve; Pêcheux, François; Wang, ZHi; Cuenot, Philippe; Neumann, Ingmar; Nguyen, Thang; Lucas, Ronan; Vaumorin, Emmanuel


IEEE design & test 32 (2015), Nr.6, S.76-86
ISSN: 2168-2356
ISSN: 0740-7475
European Commission EC
287562; VERDI
Verification for Heterogenous Reliable Design and Integration
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()

Current trend is to increase the overall use of electronic systems in daily life. Exemplarily, the complexity of automotive electronic control unit (ECU) systems is rising due to the number of components involved and the tighter interactions between these heterogeneous components (analog, digital hardware, or software), resulting in a more and more challenging verification. In this paper, we show that the universal verification methodology (UVM), initially developed for digital systems, can successfully be extended to analog and mixed signal systems. We introduce the UVM-SystemC-AMS framework for functional verification based on SystemC and its AMS extension SystemC-AMS. Using two automotive case studies, we demonstrate the flexibility of our approach both for simulation-based verification and lab-based validation using a hardware-in-the-loop (HIL) system.