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Low cost bumping by stencil printing

Process qualification for 200 mu-m pitch
: Kloeser, J.; Heinricht, K.; Jung, E.; Lauter, L.; Ostmann, A.; Aschenbrenner, R.; Reichl, H.


Microelectronics reliability 40 (2000), Nr.3, S.497-505
ISSN: 0026-2714
Fraunhofer IZM ()

Area array packages (flip chip, CSP (Chip scale packages) and BGA) require the formation of bumps for the board assembly. Since the established bumping methods need expensive equipment and/or are limited by the throughput, minimal pitch and yield, the industry is currently searching for new and lower cost bumping approaches. The experimental work of stencil printing to create solder bumps for flip chip devices is described in detail in this article. In the first part of this article, a low cost wafer bumping process for flip chip applications will be studied in particular. The process is based on an electroless nickel under bump metallization and solder bumping by stencil printing. The experimental results for this technology will be presented, and the limits concerning pitch, stencil design, reproducibility and bump height will be discussed in detail. In the second part, a comparison of measured standard deviations of bump heights as well as the quality demands for ultrafine pitch flip chip assembly are shown.