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Investigation of chip-to-chip interconnection structures for high data rates on a low cost silicon interposer

: Dittrich, Michael; Heinig, Andy

Postprint urn:nbn:de:0011-n-3663737 (614 KByte PDF)
MD5 Fingerprint: f09f0bb1e6fa3fd420aee6be0b8628de
Erstellt am: 12.11.2015

Institute of Electrical and Electronics Engineers -IEEE-:
IEEE 19th Workshop on Signal and Power Integrity, SPI 2015 : 10-13 May 2015, Berlin, Germany
Piscataway, NJ: IEEE, 2015
ISBN: 978-1-4673-6582-6
Workshop on Signal and Power Integrity (SPI) <19, 2015, Berlin>
Bundesministerium für Bildung und Forschung BMBF
IKT 2020 - Forschung für Innovation; 16M3201; ESiMED
Konferenzbeitrag, Elektronische Publikation
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()

Silicon interposers enable the heterogeneous integration of high performance systems. This paper focuses on interconnections from one chip to a neighboring chip via an interposer. We use a typical silicon interposer with polymer applied to the redistribution layer on both sides and line/space of 10 µm. We point out important advantages and differences of the chip-to-chip interconnection in comparison to usual integration using a separate package for each chip and a printed circuit board. The electrical behavior of the interconnections is simulated. The results demonstrate a 2 Gbps communication on a 9 mm long interposer interconnection. The average power consumption of a state transition of the chip-to-chip interconnection is simulated and compared to the power consumption of a typical PCB transmission line. The results show that the interposer interconnection consumes significantly more power per length than a typical PCB trace because of his increased resistance. Because of that we recommend to not decrease the line/space beyond 10 µm for chip-to-chip interconnections.