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A prototype of an AAL for high bit rate real-time data transmission system over ATM networks using a RSE CODEC

: Eilers, D.; Voglgsang, A.; Plankl, A.; Körner, G.; Steckenbiller, H.; Knorr, R.

Volltext urn:nbn:de:0011-n-364321 (79 KByte PDF)
MD5 Fingerprint: d9a3e04cd6e9539a49f2f3aa0a3fab67
Erstellt am: 5.9.2008

IEEE Computer Society:
11th International Workshop on Rapid System Prototyping : RSP 2000, June 21-23, 2000, Paris, France
Los Alamitos, Calif.: IEEE Computer Society, 2000
ISBN: 0-7695-0668-2
ISBN: 0-7695-0669-0
ISBN: 0-7695-0670-4
International Workshop on Rapid System Prototyping <11, 2000, Paris>
Konferenzbeitrag, Elektronische Publikation
Fraunhofer ESK ( IKS) ()

This work introduces a prototype of an ATM Adaptation Layer (AAL) with forward error correction (FEC) to serve the problems raised by high and variable bit rate real-time data transmission systems (for example studio/video applications) over ATM networks. To match the high bandwidth requirements at real-time and to minimize the implementation resources an encapsulated coding system is introduced. The coding system comprises a Reed Solomon Erasure (RSE) code, an interleaver and a CRC on cell level. The RSE is only capable of correcting cell-losses. Hence bit-errors are detected by the CRC and referenced as cell-losses. In using the RSE the benefits of ATM are exploited to improve FEC and the overall processing time becomes significantly small against conventional solutions. The prototype is implemented in Alteras FLEX10KE series FPGAs and the syntheses results are depicted.