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Chip in duromer technology for system in package realization

 
: Becker, K.-F.; Braun, T.; Neumann, A.; Ostmann, A.; Koch, M.; Bader, V.; Aschenbrenner, R.; Reichl, H.

European Network for the Co-ordination of Advanced Semiconductor Technologies -ENCAST-:
ENCAST Workshop 2005. Proceedings. CD-ROM : 08.-09.11.2005, Zürich
Zürich, 2005
ENCAST Workshop <2005, Zürich>
Englisch
Konferenzbeitrag
Fraunhofer IZM ()
system-in-package; encapsulation; metallization; laser structuring; embedding; chip-in-duromer

Abstract
The Chip in Duromer technology for realization of stackable SIPs, is similar to conventional Molded Interconnect Device (MID) technology, that is usually realized using thermoplastic polymers, combining the functionality of housing and substrate into one device. Advantages of the conventional MID technology are the reduction of parts during assembly by integrating mechanical and electrical functionality into a device and the reduction of space, as MID allows a 3D integration of devices. Disadvantage of conventional technology, especially if combined with typical technical thermoplastics is the large mismatch in coefficient of thermal expansion (CTE) between substrate and advanced microelectronic components as CSP or flip chip. This is reducing the applicability of thermoplastic MID to moderate temperature ranges and/or to rather robust components. To overcome this disadvantage the use of low CTE Duromer as Epoxy Molding Compounds (EMC) as base material for device assembly is proposed, generating a unique technology well adapted to SIP and MEMS packaging needs, the Duromer MID approach. The technological realization of Chip in Duromer uses equipment involved are conventional backend processes as IC bonding to Flex, transfer molding using epoxy molding compounds, laser machining, metallization and structurization processes well known from PCB processing. The use of existing equipment allows both, a rather fast process implementation and a cost effective manufacturing of the components. Within this paper a description of a generic packaging technology integrating detailed analysis of metallization processes and assembly issues. Summarized this paper presents further process development and feasibility analysis of wafer level packaging technologies for SiP solutions based on a Chip in Duromer approach.

: http://publica.fraunhofer.de/dokumente/N-36122.html