Hier finden Sie wissenschaftliche Publikationen aus den Fraunhofer-Instituten.

Side-channel analysis of a high-throughput AES peripheral with countermeasures

: Heinz, B.; Heyszl, J.; Stumpf, F.


Nanyang Technological University Singapore; Institute of Electrical and Electronics Engineers -IEEE-, Singapore Section:
14th International Symposium on Integrated Circuits, ISIC 2014. Proceedings : Singapore, 10 - 12 December 2014
Piscataway, NJ: IEEE, 2014
ISBN: 978-1-4799-4833-8
ISBN: 978-1-4799-4832-1
International Symposium on Integrated Circuits (ISIC) <14, 2014, Singapore>
Fraunhofer AISEC ()

We analyze the side-channel countermeasures implemented in a high-throughput AES peripheral of a commercially available microcontroller which is not dedicated to high security applications. We detect and classify the employed countermeasures and examine their effectiveness against first-order DPA attacks. We practically demonstrate, that all of the implemented countermeasures, which are common time-based hiding countermeasures, can easily be nullified with simple preprocessing methods. This is caused by the inherent properties of high-throughput designs (low number of cycles), which offers few choices for such countermeasures. Hence, we found that the effectively achieved side-channel protection is significantly lower than the theoretically expected one due to the way countermeasures are implemented and present ways to improve the effectiveness. We also reveal a design flaw in the implementation which allows timing-based attacks on the device.