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Hardware architecture of an Internet Protocol Version 6 processor

: Traskov, B.; Langenbach, U.; Hofmann, K.; Gregorius, P.


Shi, K. ; Institute of Electrical and Electronics Engineers -IEEE-; IEEE Circuits and Systems Society:
27th IEEE International System-on-Chip Conference, SOCC 2014. Proceedings : Las Vegas, Nevada, USA, 2 - 5 September 2014
Piscataway, NJ: IEEE, 2014
ISBN: 978-1-4799-3378-5
ISBN: 978-1-4799-3379-2
International System-on-Chip Conference (SOCC) <27, 2014, Las Vegas/Nev.>
Fraunhofer HHI ()

This paper presents the architecture of an Internet Protocol Version 6 processor for FPGA-based data processing and acquisition applications. Design choices and limitations are discussed together with a thorough simulation and verification methodology. The processor is demonstrated to frame and parse UDP over IPv6 traffic at 1Gb/s line-speed on a Virtex 5 FPGA, outperforming a reference soft-processor solution for UDP over IPv4. RTL-simulations show that 10Gb/s operation is attainable with the same architecture.