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Reconfigurable high performance architectures: How much are they ready for safety-critical applications?

 
: Sabena, D.; Sterpone, L.; Schölzel, M.; Koal, T.; Vierhaus, H.T.; Wong, S.; Glein, R.; Rittner, F.; Stender, C.; Porrmann, M.; Hagemeyer, J.

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Institute of Electrical and Electronics Engineers -IEEE-; IEEE Computer Society, Test Technology Technical Council -TTTC-:
19th IEEE European Test Symposium, ETS 2014. Proceedings : Paderborn, Germany, 26 - 30 May 2014
Piscataway, NJ: IEEE, 2014
ISBN: 978-1-4799-3416-4
ISBN: 978-1-4799-3415-7
S.175-182
European Test Symposium (ETS) <19, 2014, Paderborn>
Englisch
Konferenzbeitrag
Fraunhofer IIS ()

Abstract
Reconfigurable architectures are increasingly employed in a large range of embedded applications, mainly due to their ability to provide high performance and high flexibility, combined with the possibility to be tuned according to the specific task they address. Reconfigurable systems are today used in several application areas, and are also suitable for systems employed in safety-critical environments. The actual development trend in this area is focused on the usage of the reconfigurable features to improve the fault tolerance and the self-test and the self-repair capabilities of the considered systems. The state-of-the-art of the reconfigurable systems is today represented by Very Long Instruction Word (VLIW) processors and reconfigurable systems based on partially reconfigurable SRAM-based FPGAs. In this paper, we present an overview and accurate analysis of these two type of reconfigurable systems. The content of the paper is focused on analyzing design features, f ail-safe and reconfigurable features oriented to self-adaptive mitigation and redundancy approaches applied during the design phase. Experimental results reporting a clear status of the test data and fault tolerance robustness are detailed and commented.

: http://publica.fraunhofer.de/dokumente/N-351195.html