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Early propagation and imbalanced routing, how to diminish in FPGAs

: Moradi, A.; Immler, V.


Batina, L.:
Cryptographic hardware and embedded systems - CHES 2014. 16th International Workshop : Busan, South Korea, September 23-26, 2014; Proceedings
Berlin: Springer, 2014 (Lecture Notes in Computer Science 8731)
ISBN: 978-3-662-44708-6 (Print)
ISBN: 978-3-662-44709-3 (Online)
ISBN: 3-662-44708-8
International Workshop on Cryptographic Hardware and Embedded Systems (CHES) <16, 2014, Busan/Korea>
Fraunhofer AISEC ()

This work deals with DPA-resistant logic styles, i.e., celllevel countermeasures against power analysis attacks that are known as a serious threat to cryptographic devices. Early propagation and imbalanced routings are amongst the well-known issues of such countermeasures, that if not considered during the design process can cause the underlying cryptographic device to be vulnerable to certain attacks. Although most of the DPA-resistant logic styles target an ASIC design process, there are a few attempts to apply them in an FPGA platform. This is due to the missing freedom in FPGA design tools required to deal with the aforementioned problems. Our contribution in this work is to provide solutions for both early propagation and imbalanced routings considering a modern Xilinx FPGA as the target platform. Foremost, based on the WDDL concept we design a new FPGA-based logic style without early propagation in both precharge and evaluation phases. Additionally, with respect to the limited routing resources within an FPGA we develop a customized router to find the best appropriate dual-rail routes for a given dual-rail circuit. Based on practical experiments on a Virtex-5 FPGA our evaluations verify the efficiency of each of our proposed approaches. They significantly improve the resistance of the design compared to cases not benefiting from our schemes.