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Characterizing the chip damage potential during wafer probing of highly integrated devices

: Lorenz, G.; Stephan, T.; Petzold, M.


Beyne, Eric (General Chair) ; IEEE Components, Packaging, and Manufacturing Technology Society; Institute of Electrical and Electronics Engineers -IEEE-:
4th Electronic System-Integration Technology Conference, ESTC 2012 : Amsterdam, Netherlands, 17 - 20 September 2012
New York, NY: IEEE, 2012
ISBN: 978-1-4673-4645-0
5 S.
Electronics System Integration Technology Conference (ESTC) <4, 2012, Amsterdam>
Fraunhofer IWM ( IMWS) ()

Wafer probing is the state of-the-art procedure to test the electrical functionality of devices in semiconductor manufacturing and packaging process. During measurement, a probe tip is pressed onto the metal pad of the device with a defined force thus achieving a low-resistive and stable electrical contact. However, the contact forces have to be kept below a critical limit to avoid chip damage and to reduce the remaining scrub mark. This becomes particularly important for probing highly integrated devices with their increasingly reduced pad sizes and pitches, to maintain the wire bonding capability of the pads after testing, and when probing over active areas. It is thus important to analyze the amount of plastic deformation in the pad metal and the risk for crack initiation and chip damage during the probing process. In this study, the deformations transferred to the pad metal and the underlying active areas through probing were analyzed by finite element (FE) simulati on. For this purpose, two different bond pad metals were experimentally investigated by mechanical testing for a given probe tip geometry and displacement. In a second step reproducible scratches on bond pads were created using modified nanoindentation scratch experiments. The achieved force-displacement behavior was modeled taking into consideration the plastic material properties and large deformations during testing.