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Packaging very fast switching semiconductors

: Hoene, E.; Ostmann, A.; Marczok, C.

Energietechnische Gesellschaft -ETG-; European Center for Power Electronics -ECPE-:
CIPS 2014, 8th International Conference on Integrated Power Electronics Systems. Proceedings : February, 25-27, 2014 Nuremberg/Germany
Berlin: VDE-Verlag, 2014 (ETG-Fachbericht 141)
ISBN: 978-3-8007-3578-5
International Conference on Integrated Power Electronics Systems (CIPS) <8, 2014, Nuremberg>
Fraunhofer IZM ()

The switching speed of power semiconductors has reached levels where conventional semiconductor packages limit the achievable performance due to parasitic inductance and capacitance. Designing these parasitics intentionally is the key to overcome this speed limit. This paper gives an overview on relevant parasitic effects in semiconductor properties, package and switching cell design. A module with extremely low dc link inductance is built up using a newly developed packaging technology. The experimental results lead to a proposal for next step in package design for fast switching and minimizing EMI generation.